Placement

It is the third step in Physical design flow. During Placement, all standard cells are placed automatically on the chip core based on timing, die size and power constraints.

Placement takes place in two steps .

• Coarse/Global placement
• Legalization/Detail Placement.

During Coarse placement design gets divided into small squared equal sized boxes, called GRC's (Global Routing cells). And standard cells are just thrown inside randomly but not optimized at this stage. They may not be placed over grids and may be overlapping .

During Legalization(second step), standard cells are placed properly over grids and any overlaps are removed based on optimum timing and congestion.

If there would not be proper placement of cells than this would effect the chip performance.

Placements determines the die utilization . A typical utilization of 60% is reached after placement(depends on technology and design size). The placement follows certain boundary conditions while placing cells.They are :

1. Timing

2. Design Rule

OBJECTIVES OF PLACEMENT

• To minimize the all critical net delay.

• To minimize the total estimated interconnect length/wire length. This helps in minimizing the cost and chip size.
• To minimize the power dissipation as possible. It involves distributing the locations of standard cells components as to reduce the overall power consumption.
• To minimize the congestion. Congestion means excessive crowding. If there is less space and the standard cells are more. This is one thing which always avoid while placing standard cells.
• To minimize the power dissipation as possible. It involves distributing the locations of standard cells components as to reduce the overall power consumption.

PLACEMENT OPTIONS AVAILABLE IN THE TOOL ARE

• Congestion driven
•  Timing Driven
•  For Timing Driven placement , following timing constraints are read through SDC (Synopsis design constraint) file-
•  Clock period constraint
•  Input/Output delays
•  Uncertainty values

POST PLACEMENT CHECKS:

• During the post placement stage , we need to observe the timing report. In timing report a particular start point , end point and the rest logic between them is given.
• Observe the clock delay. Before the CTS clock should be ideal.
• Check if operating conditions(Setup, Hold Time etc.) are set.

PLACEMENT OPTIMIZATION:

We must reserve placement space for more than 5% of targeted final design utilization to ensure that there is room to add buffers and remap the network to meet timing requirement, before performing placement optimization.

The method generally adopted by tool for optimizing.

•  Adding/Deleting Buffers.
•  Remapping logic.
•  Resizing gate/Up sizing/Downsizing.

ADVANTAGES OF UP SIZING: 

• Increases speed & Driving strength.
• Up sizing means increasing the width of the transistor that is increasing the width of the diffusion. This helps to solve setup and hold violation in timing analysis.
• Because up sizing reduces the delay of the std cell. After doing up sizing standard cell become faster and after doing downsizing standard cells become slower.

SWAPPING

involves replacing a kind of threshold voltage cell with another kind.

LVT → MVT → HVT

Advantage of LVT :  Faster.

Advantage of HVT:  less Leakage power. 
Disadvantage:  LVT's has more Leakage power. We prefer LVT at timing critical part.
  
TIMING :
Until the placement and placement optimization stage the clock is ideal, all the clock pins are connected to the clock source, factors like skew , transition and the network delay assume a value 0.

Congestion Analysis:

After Placement first thing we check for Congestion ( local and global congestion) and then Timing (DRV's = transition, capacitance and fanout), utilization etc.

Definition of Congestion: When number of available routing tracks are less than the required number of tracks in particular area,it is said to be congested area.

Local congestion: when congested cells are localized in some particular area, it leads to the creation of local Hotspots i.e. highly congested area. Which is called as local congestion

Reasons: larger count of AOI/OAI cells in particular area.

High Pin density & timing critical, high utilization designs.

To do the analysis ,we need to open the congestion analysis in congestion tab over gui. Now we can see the the whole design divided into GRC's (Global routing cell). Each GRC can be highlighted with green ,red or yellow colors.

Here highly congested areas will be highlighted with red color. 

Reason may be more cell density as well as Pin density. we need to move cursor on each and every red colored GRC to know the type of cell (whether it is OAI or AOI cell) and no. of pins available on each cell.

OAI and AOI cells has more no. Of pins than their area, so called complex gates too.

For more detailed analysis, we can further check how the paths are traveling over gui. There may be the paths with single start point and multiple endpoints.

Solution: spreading out the cells and cell padding .

To do the cell padding we need to filter out the cells with no. of pins > 4 and then need to add padding for them. We can use set_keepout_margin ( ) (manual way) or through custom script which will add cell padding of 2 or 4 for filtered count of cells.

Global Congestion: when high density(cell/pin) regions are spread all over the design, it is called as global congestion.

Reasons: When cells of particular modules are not placed all together due to any reason, like bad macro placement etc.

Solution: improve macro placement and module padding/instance padding.

Padding is a method to fool the tool, just to make room available next to particular cell during timing optimization to add any buffer etc.