Sanity Checks

To make sure that all the inputs(provided by synthesis team) are complete and not erroneous, we need to ensure the correctness/quality of inputs (netlist/libs/sdc) by means of sanity checks. Few checks are listed below:

a) Netlist check: check_design -netlist


This check which verifies correctness of the netlist.

1. Input pin of a net should not be floating .It may lead to power issues or IR drop in later stages.

2. There should not be any direct connection to Vdd and Vss. It may lead to circuit burns.

3. Multi-driven nets are not allowed in the netlist.

4. No combinational loops should be there, it may lead to meta stable state.

5. There should not be any assign statement.

6. checkUnique checks whether the netlist is unique or multiple instantiation of the same module inside a netlist. It helps to avoid multiple instantiations.


b) Timing check: check_timing

Includes few checks which verifies correctness of SDC. Timing Constraints present inside SDC are given by the synthesis team and check_timing command verifies following:

• Unconstrained end points
• Missing input output delays
• Missing clock definitions
• MultiClockDriven registers

Unconstrained end points

If timing paths are unconstrained, the check_timing command only reports the unconstrained endpoints, not the unconstrained start points.

Similarly, for paths constrained only by set_max_delay, set_min_delay, or both rather than set_input_delay and set_output_delay, the check_timing command only reports any unconstrained endpoints, not unconstrained start points.

To check for unconstrained endpoints use: report_timing -exceptions

Missing input output delays and Missing clock definitions may leads to incorrect timing calculations.
set input_delay: Specifies a timing delay from one group of points to another (maybe clock signal ). Define the timing arrival at Input port when clock comes .
set_output_delay: signal must arrive at least the specified amount of time that define by command "set_output_delay" before the clock signal.


MultiClockDriven registers: where same flop get driven by more than a single clock which is logically incorrect. In such cases tool wont be able to decide the correct clock port and may lead to more than single launch and capture edges for the data. Which can further lead to setup and hold violations.


c) Library check

This check verifies, whether physical libraries are consistent with logical libraries or not. For any missing libraries check_library command will show black boxes and timing calculation will not be proper.


It checks whether the cells used in the design have been defined in the timing library.If multiple delay corners are being analyzed then each cell needs to be characterized for each corner.

check_design -physicalLibrary : checks physical libraries and reports whether all cells have its corresponding LEF views.


check_design -timingLibrary :checks whether the all cells used in the design have its corresponding timing library.