Extraction

After completion of standard cell placement and power analysis, the next phase is to route the ASIC design and perform extraction of routing and parasitic parameters for the purpose of static timing analysis and simulation.

Parasitic extraction is the calculation of all routed net capacitance's and resistances for the purpose of delay calculation, static timing analysis, circuit simulation, and signal integrity analysis.

Parasitic extraction is performed by analyzing each net in the design and taking into account the effects (such as dielectric stack) of the net’s own topology and proximity to other nets.

For calculating the Delay, we should be aware about the Resistance/Capacitance of the Network/Devices and we can extract this info (R/C) from a layout and "Parasitic Extraction do this job efficiently".

Effect of Parasitic Devices on Circuit Design:

Extra Power Consumption

Effect the Delay of circuit

Reduce the Noise Margin

Increase Signal Noise

Increase IR drop on power Supply lines

It can be used

• During Static Timing analysis
• During Noise Analysis, Crosstalk Analysis, Signal Integrity Check
• In Logic Simulation
• During IR Analysis
• Substrate Noise Analysis

So there are several ways or say mode in every Parasitic Extraction tool provided by different Vendors so that user can extract only required information. Few of them are:

• Extract Resistance(R) Only
• Extract Capacitance(C)Only
• Extract Resistance and Capacitance(RC) both

Capacitance also are of 2 types (or say "Mode") :

• Decoupled Capacitance
• Coupled Capacitance

So, we can use any combination to Decrease or Increase the Runtime. It depends on what you want and at which stage. There are 2 type of network

• Lumped Network(Lumped-C and Lumped RC)
• Distributed Network

 

Lumped capacitance is a single order approximation and considers only the total capacitance value of interconnection while ignoring the resistance value. This was used in the early days of process technology as wire delay contributions were negligible.

Lumped resistance and capacitance (or RC model) is considered to be a second-order approximation and takes into account the effect of loading capacitance as well as the total wire resistance of interconnections

 

Distributed RC Network

Distributed resistance and capacitance (or so-called pie model) is classified as a third order interconnect delay approximation. In this model, interconnections are segmented into a series of resistor and capacitor network resembling like the transmission line. 

Apart of Above extraction mode, Runtime of each Extracted Tool also depends on several parameters:

• Design Size
• Process or Technology Node
• Output format
• System Configuration (Or say available Machine Resource) like No of CPU, Memory, Machine Type.

One of the most commonly used formats used to import and export distributed RC parasitic capacitance and resistance values extracted per net based on their actual geometry and layer width and spacing information, is the Standard Parasitic Extended Format (SPEF). 

SPEF is an Institute of Electrical and Electronics Engineers (IEEE) standard.

Basics of Layout:

1. Layout can be very time consuming.

-Design gates to fit together nicely

-Build a library of std cells

-must follow a technology rule

2.Standard cell design methodology

-Vdd and GND should abut (std height)

-Adjacent gates should satisfy design rules

-nMOS at bottom and Pmos at top

-All gates include well and substrate contacts

What are Layout Extractors??

1. Once the layout is made, there always is parasitic capacitance's and resistances associated with the design.

2. This is because of the compact layouts to make the chips smaller. More you make compact layout more will it introduce these parasitic components.

3. These interferes in the functioning and performance of the circuit in terms of timing, speed and power consumption.

4. Examine interrelationship of mask layers to infer the existence o transistors and other components.

5. Related to Design Rule Checkers: design rule verification

6. Some form of layout extraction is usually done to create data for back annotation.

Tools used for extraction:

1. FastCap

2. Star-RCXT

3. QRC

4. Calibre xACT3D

Input files required for extraction

1. .def

2. qrc tech file

Outputs of extraction

1. spef

Steps to Extract a layout:

1. Create Layout CellView

2. Design Rule Checking: it will be successful when we see the results saying :"0 Total errors found".

3. Layout Parameter Extraction: mask layout contains only physical data. Extraction process identifies the devices from the layout and generates a spice like net-list and other files necessary to complete the design process.

4. Layout vs Schematic Comparison