RC Variation

RC variation is also considered as corners for the setup and hold checks. RC variation can happen because of fabrication process and the width of metal layer can vary from the desired one.

Critical corners for Setup and Hold check

We always check our chip to work in worst scenarios. We should be very pessimistic about setup and hold checks, so we consider worst case scenarios first.

Setup violation can be caused if data is coming very slow. So the condition when process is slow, voltage is minimum and temperature is maximum is the worst case for setup check.

Hold violation is caused if data comes faster. So process should be faster,voltage should be maximum and temperature should be minimum.

Now if setup and hold are checked in worst corners, then the chip should work in every scenario. Still we check them in typical corners because we need to analyze power consumption. Refer following table for the worst case scenarios for setup and hold.

In 90-nm technology and above, a timing path is predominantly governed by cell delays. And that’s the reasons only below mentioned 2 RC interconnect corners are sufficient for all the timing analysis.

1. Cbest (Also known as Cmin) – minimizes C, maximizes R

2. Cworst (Also known as Cmax) – maximizes C, minimizes R

However below 90nm node, the contribution of interconnect delay in a timing path become significant and the Coupling Cap component (Cc) in net delay can significantly alter slack values at an endpoint of a timing path. So, RC corners have to be split up as per the contribution of each component Ground Capacitance (Cg) and Coupling Capacitance (Cc). So on top of the 2 conventional RC corners Cmax and Cmin, foundry came up with 2 more RC corners.

1. RC best (also known as XTALK corner) - Cc is max , Cg x R is min

2. RC worst (also known as Delay corner) - Cc is min ,Cg x R is max

So we can say that there are overall 5 parasitic corners.

1. Cbest

2. Cworst

3. RCbest

4. RCworst

5. Typical

Few definitions/information for every corner:

1.C-best:

It has minimum capacitance. So also known as Cmin corner.

Interconnect Resistance is larger than the Typical corner.

This corner results in smallest delay for paths with short nets and can be used for min-path-analysis.

2.C-worst:

Includes corners which results maximum Capacitance. So also known as Cmax corner.

Interconnect resistance is smaller than at typical corner.

This corners results in largest delay for paths with shorts nets and can be used for max-path-analysis.

3.RC-best:

Includes corners which minimize interconnect RC product. So also known as RC-min corner.

Typically corresponds to smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than typical capacitance.

Corner has smallest path delay for paths with long interconnects and can be used for min-path-analysis.

4.RC-worst:

Includes corners which maximize interconnect RC product. So also known as RC-max corner.

Typically corresponds to larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical capacitance.

Corner has largest path delay for paths with long interconnects and can be used for max-path-analysis.

5.Typical:

This refers to nominal value of interconnect Resistance and Capacitance.

So there are 2 types of parasitic

-C-based (Capacitance dominates short wire)

-RC-based (R dominates for long wires)

In C-based C means worst and best case capacitance but in RC-based RC means worst and best case R with adjustment in C towards worst or best but keeping the process planar.

Based on the experience it was found that C-based extraction provides worst and best case over RC for internal timing paths because Capacitance dominates short wire. However for large design, inter-block timing paths were often worst with RC worst parasitic since R dominates for long wires.

Note: No corner guarantees min or max delay for an arbitrary transistor driving an arbitrary wire topology

With the help of below picture, we can understand easily :

Extraction

After completion of standard cell placement and power analysis, the next phase is to route the ASIC design and perform extraction of routing and parasitic parameters for the purpose of static timing analysis and simulation.

Parasitic extraction is the calculation of all routed net capacitance's and resistances for the purpose of delay calculation, static timing analysis, circuit simulation, and signal integrity analysis.

Parasitic extraction is performed by analyzing each net in the design and taking into account the effects (such as dielectric stack) of the net’s own topology and proximity to other nets.

For calculating the Delay, we should be aware about the Resistance/Capacitance of the Network/Devices and we can extract this info (R/C) from a layout and "Parasitic Extraction do this job efficiently".

Effect of Parasitic Devices on Circuit Design:

Extra Power Consumption

Effect the Delay of circuit

Reduce the Noise Margin

Increase Signal Noise

Increase IR drop on power Supply lines

It can be used

• During Static Timing analysis
• During Noise Analysis, Crosstalk Analysis, Signal Integrity Check
• In Logic Simulation
• During IR Analysis
• Substrate Noise Analysis

So there are several ways or say mode in every Parasitic Extraction tool provided by different Vendors so that user can extract only required information. Few of them are:

• Extract Resistance(R) Only
• Extract Capacitance(C)Only
• Extract Resistance and Capacitance(RC) both

Capacitance also are of 2 types (or say "Mode") :

• Decoupled Capacitance
• Coupled Capacitance

So, we can use any combination to Decrease or Increase the Runtime. It depends on what you want and at which stage. There are 2 type of network

• Lumped Network(Lumped-C and Lumped RC)
• Distributed Network

 

Lumped capacitance is a single order approximation and considers only the total capacitance value of interconnection while ignoring the resistance value. This was used in the early days of process technology as wire delay contributions were negligible.

Lumped resistance and capacitance (or RC model) is considered to be a second-order approximation and takes into account the effect of loading capacitance as well as the total wire resistance of interconnections

 

Distributed RC Network

Distributed resistance and capacitance (or so-called pie model) is classified as a third order interconnect delay approximation. In this model, interconnections are segmented into a series of resistor and capacitor network resembling like the transmission line. 

Apart of Above extraction mode, Runtime of each Extracted Tool also depends on several parameters:

• Design Size
• Process or Technology Node
• Output format
• System Configuration (Or say available Machine Resource) like No of CPU, Memory, Machine Type.

One of the most commonly used formats used to import and export distributed RC parasitic capacitance and resistance values extracted per net based on their actual geometry and layer width and spacing information, is the Standard Parasitic Extended Format (SPEF). 

SPEF is an Institute of Electrical and Electronics Engineers (IEEE) standard.

Basics of Layout:

1. Layout can be very time consuming.

-Design gates to fit together nicely

-Build a library of std cells

-must follow a technology rule

2.Standard cell design methodology

-Vdd and GND should abut (std height)

-Adjacent gates should satisfy design rules

-nMOS at bottom and Pmos at top

-All gates include well and substrate contacts

What are Layout Extractors??

1. Once the layout is made, there always is parasitic capacitance's and resistances associated with the design.

2. This is because of the compact layouts to make the chips smaller. More you make compact layout more will it introduce these parasitic components.

3. These interferes in the functioning and performance of the circuit in terms of timing, speed and power consumption.

4. Examine interrelationship of mask layers to infer the existence o transistors and other components.

5. Related to Design Rule Checkers: design rule verification

6. Some form of layout extraction is usually done to create data for back annotation.

Tools used for extraction:

1. FastCap

2. Star-RCXT

3. QRC

4. Calibre xACT3D

Input files required for extraction

1. .def

2. qrc tech file

Outputs of extraction

1. spef

Steps to Extract a layout:

1. Create Layout CellView

2. Design Rule Checking: it will be successful when we see the results saying :"0 Total errors found".

3. Layout Parameter Extraction: mask layout contains only physical data. Extraction process identifies the devices from the layout and generates a spice like net-list and other files necessary to complete the design process.

4. Layout vs Schematic Comparison

Routing

After completion of standard cell placement and power analysis, Routing is the next phase. Extraction of routing and parasitic parameters for the purpose of static timing analysis and simulation will be followed.

As ASIC designs are getting more complex and larger,routing is becoming more difficult and challenging. It is possible for routing to fail to complete, or to take an unacceptable amount of execution run time.

Besides the routing algorithms, the factors which influence the routability of a given ASIC are the layout of standard cells style, a well-prepared floorplan and the quality of standard cell placement as discussed in previous chapters.

Due to the inherent complexity of ASIC designs and the very large numbers of interconnections associated with them, the overall routing is performed in three stages: special routing, global routing and detail routing.

1. Special Routing

Special routing is used for standard cells, macro power, and ground connections. Most special routers use line-probe algorithms. The line-probe method uses line segments to connect standard cells, macro power, and ground ports to ASIC power and ground supplies.

2. Global Routing

Global routing is the decomposition of ASIC design interconnections into net segments and the assignment of these net segments to regions without specifying their actual layouts. Thus, the first step of the global routing algorithm is to define routing regions or cells (i.e. a rectangular area with terminals on all sides) and calculate their corresponding routing density.

These routing regions are commonly known as Global Routing Cells (GRC's).

 

Global routing algorithms generate a non-restricted route (i.e. not a detail route) for each net in the design and use some method of estimation to compute wire lengths and extract their corresponding parasitics.

After global routing is performed, the pin locations will be determined such that the connectivity among all standard cells in the ASIC core area is minimal. Almost all global routers report the design routability statistic using overflow or underflow for Global Routing Cells (GRC), which is the ratio of routing cells’ capacity and the number of nets that are required to route a given routing cell for all vertical and horizontal routing layers.

3. Detail Routing

The objective of detail routing is to follow the global routing and perform the actual physical interconnections of ASIC design. Therefore, the detail router places the actual wire segments within the region defined by the global router to complete the required connections between the ports.

Detail routers use both horizontal and vertical routing grids for actual routing. The horizontal and vertical routing grids are defined in the technology file for all layers that are being used. The detail router can be grid-based, gridless-based, or subgrid-based.

Grid-based routing imposes a routing grid (evenly spaced routing tracks running both vertically and horizontally across the design area) that all outing segments must follow.

In addition, the router is allowed to change direction at the intersection of vertical and horizontal tracks as indicated.

The advantage of grid-based routing is efficiency. When using a grid-based router, one needs to make sure that the ports of all instances are on the grid.

Otherwise, they can create physical design rule errors and will be difficult to resolve with the router.

Gridless-based (or shape-based) routers do not follow the routing grid explicitly, but are dependent on the entire routing area and are not limited by grid’s restrictions. They can use different wire widths and spacing without routing grid requirements. The most fundamental problem with this type of router is that they are very slow and can be very complicated.

The subgrid-based router brings together the efficiency of grid-based routers with the flexibility (of varying the wire width and spacing) of the gridless-based routers. The subgrid-based router follows the normal grid similar to the grid-based router. However, a subgrid-based router considers these grids only as guidelines for routing and is not required to use them.

This procedure of detail routing is very similar to global routing. The only difference is that during detail routing, physical wire segments will be used for connection rather than connectivity projections. Thus, it is important to have strong correlation between the detail and global routers with regard to the wire length approximation and actual wire connection.

The reason for the close correlation between global and detail routers is that one can determine whether the ASIC design timing meets actual timing requirements by estimating the wire resistance and capacitance early on in the physical design cycle.